CSAPP 01.5 - Memory Hierarchy & Cache Memories - Locality Simulator
"To deal with the processor–memory gap, system designers include smaller, faster storage devices called cache memories that serve as temporary staging areas for information that the processor is likely to need in the near future."
— CS:APP (Computer Systems: A Programmer's Perspective), Section 1.5
⚙️ Overview
This interactive memory hierarchy simulator demonstrates the fundamental system principle that Storage Devices Form a Hierarchy, where storage at each level serves as a cache for the level below. It visualizes the physical trade-offs between access latency, capacity, and cost per byte across seven distinct memory tiers, tracking how data words and cache blocks filter upward to bridge the processor–memory speed gap in real time.
🔬 The 7 Hierarchy Levels & Latency Tiers
- L0: CPU Registers (Regs): Residing directly on the processor chip, registers hold 64-bit words retrieved from cache memory with zero or single-cycle access latency (< 1 ns).
- L1: L1 Cache (SRAM): On-chip static RAM with tens of thousands of bytes, holding 64-byte cache lines fetched from L2 cache with near-register speeds (2–4 cycles, ~1 ns).
- L2: L2 Cache (SRAM): Larger SRAM array (hundreds of KB to several MB) connected via specialized buses, caching lines from L3 with 10-cycle latency (~3–5 ns).
- L3: L3 Cache (SRAM): Shared multi-megabyte on-chip cache serving multi-core processors, staging cache lines retrieved from main memory in 30–50 clock cycles (~10–20 ns).
- L4: Main Memory (DRAM): Dynamic RAM storing gigabytes of physical address space, holding virtual memory pages and 4KB disk blocks retrieved from local disks across 100–200 clock cycles (~50–100 ns).
- L5: Local Secondary Storage (Disks): High-capacity local disks (NVMe SSDs / SATA HDDs) holding filesystem blocks retrieved from remote servers across hundreds of thousands to millions of cycles (~10 μs–10 ms).
- L6: Remote Secondary Storage (Cloud / Web): Distributed network file systems and Web servers providing virtually unlimited archival capacity across wide-area networks at high latencies (> 100,000,000 cycles, ~10–200 ms).
🕹️ Interactive Features
- Upward Data Filtering Pipeline: Input customized program data or string payloads (such as
"hello, world\n") and execute step-by-step upward caching, observing physical chunk distillation from coarse disk/network blocks down to 64-bit register words. - Dynamic Teleprompter & HUD Telemetry: Real-time telemetry tracking access latency scales, clock cycle gaps, storage media hardware, and active cache line allocations across the memory pyramid.
📚 Academic Reference
- Book: Computer Systems: A Programmer's Perspective (3rd Edition)
- Chapter: Chapter 1: A Tour of Computer Systems
- Section: 1.5 Caches Matter & 1.5.2 Storage Devices Form a Hierarchy
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